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veripower
AI-assisted IC design flow skills — specification, RTL, lint/CDC, simulation, synthesis, timing analysis, and signoff
chipweaver6
4 results
AI-assisted IC design flow skills — specification, RTL, lint/CDC, simulation, synthesis, timing analysis, and signoff
规格驱动开发:写代码前先写结构化 spec(目标/边界/验收标准),分阶段门控推进。受 addyosmani/agent-skills(88k★ MIT)启发。
Five-stage specification-driven development workbenches for DeepSeek Harness Web.
规格门插件:模糊需求访谈暴露假设(歧义评分收敛)+ 不可变 Seed 规格锁定 + 交付前验收门。借鉴 Ouroboros 访谈门/三段验证思想,与 dsh-cybernetics 协同(验收失败事件喂控制论回路)。